Pipelined cache memory arrays used for microprocessors utilize self-resetting features for maximum performance. However, when multiple reads or writes need to be performed in a cycle, these features are found to be unacceptable. In high density cache memory arrays, accesses must be maintained within clock speeds. Current design of sensing schemes utilizes self-timed sensing from word or dummy word lines selections.
U.S. Pat. 5,058,062 by Y.Wada et al, which issued on Oct. 15, 1991, discloses a memory circuit wherein a bit line and a dummy bit line are connected to reset and set terminals of a sense amplifier circuit.
In U.S. Pat. No. 4,339,809 by R. G. Stewart, which issued on Jul. 13, 1982, there is disclosed a memory circuit wherein a transition detector receiving an input from memory addresses provides a pulse which passes through delay circuits to control the operation of sensing circuits.
Prior art small signal memory designs utilizing sensing schemes which are enabled by signals used to mimic or are patterned after the voltage and timing of word lines in memory arrays are indicated in a block diagram show in FIG. 1 of the drawings. FIG. 1 illustrates a sensing scheme wherein a dummy word line and dummy bit line pairs in a memory array are activated at the same time as the normally selected word and bit lines. These signals are then used to enable a sense latch along with late select signals which are generated by any appropriate known type of directory, such as from virtually or physically indexed caches. Referring to FIG. 1 in more detail, at the beginning of a clock cycle when the clock CLK is positive, array word addresses are applied to a word address decoder 10 which selects one of the word lines WL1 to WLn of memory cache array 12, driven by associated word drivers D1 to Dn, respectively, as well as selecting the dummy word line DWL driven by dummy word driver DD.
The array 12 includes a plurality of memory cells 14 and a plurality of pairs of bit lines BLT0,BLC1, BLT1,BLC1 through BLTn,BLCn and dummy bit line pair DBLT,DBLC arranged orthogonal to the word lines WL1 to WLn and DWL. The cells 14 are disposed at the intersections of the word lines and the pairs of bit lines. With the dummy word line DW1 and, e.g., word line WL1 selected, voltage differentials begin to develop on the dummy bit line pair DBLT,DBLC and on, e.g., bit line pair BLT0,BLC0. When the voltage differential is developing on the bit line pair BLT0,BLC0, a late select signal LSS0, derived from decoded bit line addresses, is applied to a timing circuit 16 to which is also applied an inverted clock ICLK generated from clock CLK through an inverter I, providing at the output of the timing circuit 16 a signal LS0. The signal LS0 is applied to a bit switch BS1 which turns on to couple the bit line pair BLT0,BLC0 to the input SAT and SAC of a differential sense amplifier SA.
Meanwhile, the signal being developed on the dummy bit line pairs DBLT,DBLC is applied to the input of a delay circuit 18 which supplies from its output set signal S to turn on the sense amplifier SA which senses the voltage differential developed across the bit line pair BLT0,BLC0. The delay circuit 18 is generally designed to apply the set signal S to the sense amplifier SA only after the signal on the pair of bit lines BLT0,BLC0 is large enough, as generally prescribed by process, environment and performance, to be sensed by the sense amplifier SA. It should be noted that had a cell 14 been selected which was to be developed on bit line pairs BLT1,BLC1, a late select signal LSS1 would have been applied to timing circuit 20, similar to that of timing circuit 16, to turn on the bit switch BS2. It can also be understood that the late select signals LSS0 and LSS1 are derived, as is known, from bit line addresses after they have been decoded.
It can be seen that in this prior art sensing technique the sense amplifier SA is always turned on at a fixed time after a word address is applied to the word address decoder 10 via the dummy circuits. Although this sensing technique has been used successfully, it is not satisfactory for some applications. For example, this prior art sensing technique can not be used satisfactorily in some applications since the late select signals arrive late in the cycle, thus, an incorrect read operation would occur. Accordingly, bit switches located after sense latches require a sense latch for each bit switch, decreasing array utilization.